The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for optimizing energy efficiency in multicore processors under quality of service (QoS)/performance constraints.
Dynamic voltage and frequency scaling (DVFS) is a popular technique for power saving in a computing system. If the throughput required of a processor is low, clock frequency and the supply voltage may be reduced while maintaining throughput. In multicore processors, another option for power saving is to consolidate work to a subset of processor cores, allowing the remaining unused cores to be put in a deep sleep state or power gated, which may be referred to as core folding. Interestingly, core folding is orthogonal to and may be combined with DVFS to maximize power savings. As technology progresses, power saving techniques like core folding may become increasingly important, due to the reduction in the overall DVFS range.